The present invention relates to a spread spectrum telecommunication and in particular to a synchronization circuit with correlated signal used in the spread spectrum telecommunication using a direct spreading method.
The spread spectrum telecommunication has been recently put into practice and has an advantage over general narrow-band telecommunication in that it has a high immunity from multi-path and/or non-white noise.
In a system for accomplishing such direct spread spectrum telecommunication, it is necessary to conduct a spreading and despreading operations in the modulation and demodulation stages, respectively.
In an example of a receiver in such a system, a received incoming signal is converted from a RF (radio frequency) signal to an IF (intermediate frequency) signal. By processing circuits for processing the signal after it has been converted into IF signal, the IF signal is split by means of a splitter into two signals, which are then multiplied with a cosine and sine components of a local signal from a local oscillator by means of multipliers, respectively. Signals from the multipliers are input to two correlators as an I and Q signals of respective base band components, respectively. These correlators have codes which are preset to correlate with spread codes which have been spread by a transmitter. A correlation relationship between the present codes with the spread codes is established in the correlators so that I and Q correlated signals are output therefrom, respectively.
Thereafter, they are demodulated in demodulating units. At this end, it is necessary to input the I and Q correlated signals to the demodulating unit in synchronization of the correlated signals. The circuit for this synchronization is referred to as synchronizing unit with correlated signals.
In order to establish a synchronization relationship, a root of the sum of the squares of the outputs from I and Q correlators is determined by a root-of-sum-of-squares circuit to provide an output of the absolute value of the correlated signals.
The correlated signals represent signals in the form of spike, which are generated in a timing of high correlated relationship. These signals are referred to as correlation spikes. The correlation outputs of the I and Q signals per se assume values which are on curves represented by positive and negative sine and cosine functions. The root of the sum of the squares, that is I.sup.2 +L +Q.sup.2 +L assumes a constant value at its peak. This is due to the fact that there is a relation sin.sup.2.theta.+cos.sup.2.theta.=constant.
Accordingly, the synchronization circuit with correlated signals synchronizes with a desired signal by using a signal representing the root of the sum of the squares to provide synchronizing pulses.
A synchronization circuit with correlated signals which is similar to the frame synchronizing system of the general digital wireless telecommunication system is used as the synchronization circuit with correlated signals of the above-mentioned direct spread telecommunication system.
The synchronization circuit used for the general frame synchronization circuit is disclosed in, for example, {character pullout}(Kimio Tanaka) "{character pullout}{character pullout}(Digital Telecommunication Technology)", published by {character pullout}{character pullout}(Tokai University Publishing Association).
There's a synchronization circuit with correlated signals in a receiver of the prior art spread spectrum telecommunication system, which is similar to the synchronization circuit for the general frame synchronization, which is exemplified above.
The prior art synchronization circuit with correlated signals comprises a discriminator, initial synchronization circuit, synchronizing counter, AND circuits, error lock counter, correct lock counter and so on.
In this synchronization circuit with correlated signals, the discriminator compares the correlated signal C which is obtained as the root of the sum of the squares with a predetermined threshold. If the correlation signal C exceeds the threshold, the discriminator determines that the correlation is so high that the signals are synchronized for generating synchronizing pulses (correlated signal detection pulses) SP.
The initial synchronization circuit confirms that several detection pulses have been consecutively generated at positions of the correlation spikes (each period of code) and enables the synchronization counter to operate after determining that the initial synchronization is achieved.
This causes the synchronization counter to individually count the synchronization of the next correlation spikes.
An AND logical operation between the output of the synchronization counter and the correlation pulse SP from the discriminator is conducted by an AND circuit.
If the signals are synchronized with each other at appropriate positions, signals would be generated from the synchronization counter in a timed relationship in which next correlation spike would be generated when considering the initial synchronization timed relationship. On the other hand, the correlation detection pulses SP are generated at positions of correlation spikes. Agreement between two signals is determined by the AND circuit. When they agree, the circuit generates a count pulse CP for counting up the correct lock counter.
Since the two signals do not agree when the initial synchronization is erroneous, the circuit counts up the error lock counter. If the initial synchronization is appropriately conducted in such a manner, a correct synchronization with correlation would be kept. If it is improperly conducted, the error lock counter would exceed a preset value to determine that it is in an erroneous synchronization relationship for resuming the initial synchronization relationship.
As mentioned above, in the prior art, a determination was made based upon a threshold whether correlation outputs are correlated to each other and it is determined that there is a correlation therebetween if the correlation output exceeds the threshold.
The difference of the outputs between the case in which a correlation is established and the case in which no correlation is established is large when the spread factor is high. Recently, spread code having a spread factor which is in order of about 10 may be used. In this case, the output difference between the above-mentioned cases would be small.
Even if the number of samples is increased in view of a low spread factor, the increase in scale of the circuits such as correlator and the like is less. Accordingly, the number of samples may be increased from two samples per one chip to three or four samples per one chip.
There exemplifies sample points in a period of time when the correlation value along a correlation output curve in its upper part exceeds the threshold. Three samples and five samples exceed the threshold for during one correlation spike due to the fact that the spread factor is low and the number of samples is increased in cases of three samples per one chip and five samples per one chip. The prior art circuit has a drawback that the sample which previously exceeds the threshold would be synchronized so that a sample which does not correspond to higher correlation spike is synchronized.
A multiplexing system in the spread spectrum communication is disclosed in Japanese Patent Application No. 7-206159, the inventors and applicant of which are identical to those of the present application, respectively.
There will be described a transmitter system in the multiplexing system.
A data signal is differentially coded by a differential coding unit and then converted into four parallel signals P1 to P4 by a serial/parallel converter.
The parallel signals P1 to P4 are multiplied by spread codes from a PN generator by multipliers to provide independent spread signals M1 to M4, respectively. After the signals M1 to M4 are differently delayed by delay elements, respectively, they are mixed by a mixer and then the mixed signal is modulated by a multi-value modulator having an local oscillator and is frequency-converted by a frequency converter and is transmitted to air after being amplified by a power amplifier. This causes a number of signals which are serial/parallel converted to be multiplexed for transmission. Although the signal is converted into four parallel signals, the number of the signals may be optionally preset when the number of signals to be multiplexed is preset.
A case in which the thus transmitted signal is received and is passed through the correlator will be considered.
Since the multiplexed signals are the sum of individual independent signals, the output from the correlator is the linear sum of the outputs which are obtained when respective signals are passed through the correlator.
There exemplifies a case of multiplexing of 5 signals unlike that of 4 signals. The Barker code of 11 chips is used as a spread code.
In this case, the correlation value largely varies in a range of 7 to 15 (absolute value).
Accordingly, it is necessary to decrease the threshold so that the correlation value exceeds the threshold even when it is 7. By do so, the correlation value exceeds the threshold over several samples when it assumes 15. There is the higher risk that erroneous synchronization may occur than the previous case.
Another problem which may occur in the prior art will also be described.
It is assumed that a correlation flag be set at the position where the correlation is highest.
In this case, the signals (multiplexing of 5 signals) would be to be equally delayed by 11/5. It is difficult for the digital circuit to provide an equal delay time. The signals would be delayed by multiples of an integer of the number of chips. The signals would be delayed by 2, 2, 2, 2 and 3 chips in this case.
Such delaying by multiples of the integer of the chip is readily applicable in embodying the invention which is disclosed in Japanese Patent Application No. 8-13963, the inventors and the applicant of which are identical to those of the present application.
The correlation output in such a case becomes an output in which respective outputs of five signals are multiplexed. A case in which the root of the sum of the squares of the outputs is calculated and the result is output will be considered.
The timing relationship of the correlation have to be 2, 2, 2, 2, 3 similarly to the transmitter side. In order to make difference among the timing signals on demodulation, it is necessary to establish a synchronization relationship with correlation in synchronization with a signal representing the leading edge of multiplexed block.
However, in the prior art synchronization circuit with correlated signals timing signals of the correlation are generated by the synchronization circuit with correlated signals and confirmation of the synchronization is conducted by comparing the signals exceeding the threshold with the timing signals.
An example of synchronization pulses which are generated by the synchronization circuit with correlated signals which operates in such a manner exemplified by the case using multiplexing of 5 signals.
In this case, coincidence of synchronization is determined when 3 pulses are consecutively generated in the initial synchronization. Accordingly, the relationship of FIG. 8A or FIG. 8B meets the requirement so that the signals may be synchronized in an erroneous timing relationship as is shown by this example.
Even if the number of the consecutive pulses is increased to 8, for example, in order to avoid this erroneous synchronization, coincidence may not occur at most twice and may occur 6 times. There is still the risk that erroneous synchronization may occur if two signals exceed the threshold due to noise.
Since coincidence occurs four times whereas incoincidence occurs twice, the number of the counts of the incoincidence is always lower than that of coincidence. If the number of the incoincidence is decreased to preset the number of overflows. the possibility of the erroneous synchronization may increase even if the signals are synchronized at appropriate positions.
This is due to the fact that the signal exceeds the threshold at least five times for a period of multiplexing.
The prior art synchronization circuit has problems that initial synchronization is unstable and that it is difficult for a synchronization holding circuit to properly function even if the signals are synchronized at incorrect positions.